Highly integrated semiconductor circuits are increasingly important, particularly in producing battery operated devices such as cell phones, portable computers such as laptops, notebook and PDAs, wireless email terminals, MP3 audio and video players, portable wireless web browsers and the like, and these integrated circuits increasingly include on-board data storage. As is known in the art, such data storage may take the form of dynamic memory in which arrays of cells are provided, each cell is a storage capacitor formed with an associated adjacent access transistor. Dynamic memory offers excellent density and minimum required silicon area, however the need to frequently refresh the storage cells, and the loss of the stored data on power loss, makes this type of data memory less attractive in some respects, particularly for battery operated devices. Static RAM memory is therefore increasingly being incorporated into these large ICs, sometimes called “SOCs” or “systems on a chip”. Typical applications for these embedded SRAMs or “e-SRAM” include for use as fast memory adjacent a processor such as cache memory, as register files, as fast scratchpad memory, for data pipelining or time conversion operations such as FIFOs, and for use in buffering applications such as frame buffers. SRAM offers two important and obvious advantages over DRAM, first, the data is available faster than for DRAM; and second, static RAM retains its stored data when power is lost. SRAM is particularly attractive when designing portable battery-operated equipment where it is expected that power will suddenly be lost as the battery becomes exhausted.
In conjunction with the increasing use of SRAMs embedded with various other logic circuitries on a single integrated circuit, (for example, ASIC or FPGA type integrated circuits) process technologies for manufacturing of integrated circuits continue to shrink. As the scaling of the dimensions of CMOS integrated circuitry gets smaller, certain dominant problematic effects such as the threshold voltage (Vt) mismatch occur including increased sub threshold leakage currents. These effects cause the minimum supply voltage Vcc required to correctly store and retrieve data in an embedded SRAM array (usually called “Vcc, min”) to become a critical supply voltage limit. Thus for the proper programming and retention of data stored in an embedded static RAM block, a fairly high Vcc, minimum voltage has to be maintained. This in turn leads to undesirably larger power consumption, especially during stand-by cycles when the SRAM is not being actively operated. A known measure of this power consumption is the standby current, usually referred to as Isb. It is desirable therefore to reduce Isb to the minimum possible level, and this in turn creates a need to reduce the Vcc, min voltage supplied to the SRAM array.
Further, and as is often the case in the manufacture of semiconductor circuits, increasingly various functions are being integrated together into a single integrated circuit device to provide a total solution or system in one, or a few, integrated circuits. The use of embedded SRAM circuits is increasing, where an SRAM block including the associated peripheral driver circuitry, e.g. word line drivers, decoders, sense amps, column decoders and the like, are included in a library of verified reusable design functions which may be placed onto a single semiconductor device with other memory cells, logic cells, processor blocks such as ARM, DSP, microprocessor, or bus controller logic circuits, clocking circuitry, and so forth. This type of SRAM design may be described as an “ASIC library memory” or an e-SRAM (embedded SRAM). By including the embedded SRAM block with various other user defined functions implemented in logic circuitry, these integrated circuits incorporate many functions into a single SOC for use in a cellular phone, PDA, personal music player, laptop computer, portable wireless email terminal, etc.
A paper by Y. Nakagome et al. entitled “Review and Future Prospects for Low Voltage RAM Circuits”, IBM Journal of Research and Development, Vol. 47, No. 5/6, pp. 525-552, September/November 2003, describes an industry estimate that these embedded memory functions may soon occupy more than 90% of the area of these Systems on a Chip (SOCs) integrated circuits. Thus the power consumption in these embedded SRAM memories is particularly important, and there is an ongoing need to reduce the power used in these SRAM memory blocks to as low a level as possible.
FIG. 1 depicts a typical prior art 6T SRAM cell comprised of four MOS transistors coupled to form a latch, and two MOS pass gates which selectively couple the data lines or bit lines to the cell, the data is passed into or out of storage nodes within the cell. Because the cell is a static RAM cell, the data will be retained as it was last stored, that is, the cell will remain as it was last programmed. U.S. Pat. No. 7,023,056, titled “Memory Cell Structure”, assigned to the assignee of the present application and herein incorporated by reference, describes layout and semiconductor structures for efficiently providing both 6T SRAM cells as shown in FIG. 1, and similar 8T SRAM cells with dual ports, such as may be used for register files.
In operation, bit lines BL and BL_ of FIG. 1 are typically arranged in parallel and span an array of SRAM cells as either rows, or columns, with the cells arranged between them. Word lines WL (only one is shown) are typically ranged orthogonal to, and often perpendicular to; the bit lines BL (sometimes called data lines or DL) and form columns, or rows, respectively. Decoders and drivers not visible in FIG. 1, but described later herein, form so-called “peripheral” circuits that selectively activate the word lines and the bit lines to provide READ operations, where data stored on nodes A and B is provided to the bit lines BL and the complementary bit line BL_ by providing a word line voltage on WL sufficient to cause the pass gates PG1 and PG2 to couple the storage nodes to the bit lines. The state of the storage nodes will cause a differential voltage to form on the bit lines BL, BL_ which may represent either a logical one or logical zero state, the differential voltage is sensed by sense amplifiers (not visible in FIG. 1) that are coupled to the bit lines BL and BL_ as is known in the art. Similarly, for a WRITE operation, driver circuits that are coupled to the bit lines BL and BL_ provide complementary input data, which is coupled to the storage nodes of a selected DRAM cell. This is accomplished by providing a voltage at the word line WL that causes the pass gates PG1 and PG2 to couple the respective bit lines to the storage nodes node A and node B, the bit line drivers are designed with sufficient drive strength to overdrive the transistors MP1, MP2, MN1, MN2 which form a latch that is the static RAM cell. In this manner the drive circuits can program the storage nodes node A and node B with the data presented on the bit lines BL and BL_ during the write operation.
FIG. 1 shows only a single SRAM cell formed of 6 transistors, e.g. a “6T” cell. Practical SRAM blocks will include many thousands of these cells arranged in rows and columns with a plurality of bit lines and word lines arranged between them to form a SRAM cell array.
FIG. 2 (an illustrative and non-limiting example) depicts a portion of such an array as is known in the art, with four 6T SRAM cells as shown in FIG. 1. Each of the four cells labeled Cell 00, Cell 01, Cell 10, Cell 11 is an instance of, and identical to, the cell of FIG. 1. In FIG. 2, word line WL0 is coupled to and traverses Cells 00 and 01, word line WL1 is coupled to and traverses Cells 10, 11, bit lines BL0 and BL0_ are provided on either side of and are coupled to Cells 00, 10, and bit lines BL1 and BL1_ are provided on either side of, and are coupled to, Cells 01 and 11. To access a particular cell, it can be seen that the corresponding word line can be activated while the corresponding bit lines are either observed for a READ operation, or driven with input data for a WRITE operation. Sense amps (not shown) coupled to the complementary bit lines are used to sense the READ data, which appears in the form of a small differential voltage measured across the bit line pair, as is known in the art. Drivers (not shown) coupled to the bit lines likewise provide WRITE data on the respective bit line pairs for WRITE operations. Each SRAM cell has a row and column address and therefore may be individually addressed by a row decoder which provides an active voltage on one of the word lines, and a column decoder which activates the appropriate sense amp or bit line drivers on one of the bit line pairs, in this manner each storage cell has a unique physical address. The peripheral circuitry therefore provides the data input, data output, decoding, and sense amplifiers required for the surrounding circuitry to store data in, and access data from, the static RAM cells.
A prior art approach to addressing the power consumption and Vcc problem in an embedded SRAM (such as is shown in FIG. 2) is to provide varying supply voltages to the cells and bit lines in the SRAM array during the different operations. FIG. 3 depicts one example of this prior art approach. This implementation is described in U.S. Pat. No. 6,891,745, titled “Design Concept for SRAM Read Margin”, to J. J. Liaw, which is also assigned to the assignee of the present application and which is herein incorporated by reference. FIG. 3 illustrates in a plan view the major blocks of the SRAM peripheral circuitry and the SRAM cell array to form SRAM 301.
In FIG. 3, sense amp and bit line decoders 303 are coupled to the bit lines BL (0:m) and BL_(0:m) to form a number of columns m+1 in the SRAM cell array 305. Word line driver circuitry 307 is provided and coupled to the word lines WL (0:n). Each word line forms a “row” in the array. Thus the array is an m+1 by n+1 cell array and an SRAM cell such as the one depicted in FIG. 1 is positioned at each word line, bit line intersection within the array.
In FIG. 3, an additional element is shown coupled to the word lines; this is a voltage generator labeled Vcc Select 309 that has outputs Vcc (0:n). This added circuitry provides an independent and dynamic supply voltage Vcc to each row of cells within the array. A decode operation is performed and the supply voltage is kept at an initial low voltage Vdd for all cells, however during READ operations, the selected cell row is provided with an enhanced supply voltage of Vdd+VPU (a pumped voltage over Vdd). This voltage may exceed the Vdd voltage by a multiple of 1.05 to 1.3. Write operations are conducted at the lower voltage Vdd, which improves the static noise margin (SNM) for write operations. Thus the array may be maintained at a lower operational supply voltage, however the row of cells being read during a READ operation are supplied with the higher voltage. This higher supply voltage increases the SRAM cell static noise margin (SNM) to acceptable levels that are not otherwise possible with the lower supply voltage. This prior art approach also requires that in the decoding circuitry associated with the cell array, the circuitry usually referred to in the art as the “peripheral circuitry” or “peri”, a “y-select” circuit is implemented to selectively provide different positive voltage levels Vdd to the selected rows of cells in the array during the reads. A pump or boost circuit is also needed to form the higher supply voltage Vdd+VPU. This prior art approach thus adds silicon area to the SRAM array and to the peripheral circuitry, which is undesirable as it reduces the amount of storage that can be provided in the embedded SRAM for a given application.
Another similar proposed approach is described in a paper entitled “0.4-V Logic Library Friendly SRAM Array using rectangular diffusion cell and delta boosted array voltage scheme”, by Masanao Yamaoka et al, 2002 Symposium on VLSI Circuits, Digest of Technical Papers which publication is herein incorporated by reference. In this scheme, the supply voltage provided to the SRAM cell array for an embedded SRAM function is boosted over the Vdd level during active cycles, but is placed at a lower standby voltage during inactive cycles. This approach also requires a boost voltage generator which requires additional area and significant circuit complexity, in addition, the load transistors (P type) and the driver transistors (N type) in the SRAM cell have to be formed with specific different thresholds, to improve the noise margin operation of the SRAM cell during WRITE operations.
Table 1 depicts voltages used during the operation of an SRAM array with the “y-select” prior art approach to the Vcc minimum problem.
TABLE 1CellCellPeripheralArea VddArea BLCircuitOperationCVddVddcVddpNoteREADHighLowLowRequires y selectVddp + 10%Vddp − 10%Vdd − 10%circuit, 20% areaWRITELowHighLowpenaltyVddp − 10%Vddp + 10%Vdd − 10%
From Table 1, the voltages applied during a READ cycle are Vddp+10% for the cell area, Vddp−10% for the bit line driver, and Vdd−10% for the peripheral circuits. For the WRITE cycle, the voltages are Vddp−10% for the cell area, and Vddp+10% for the bit line drivers, while the peripheral circuitry remains at Vdd−10%.
Table 2 shows a power consumption and area penalty comparison for different design solutions. In Table 2, an SRAM array is shown with no power reduction, and is compared with the reduced power solution of the prior art. For the area penalty concern, the prior art reduced power solutions require added logic circuitry and decoders, typically referred to as “y select” circuitry, and additional voltage booster or pump circuitry, to provide these required dynamic supply voltages to the various SRAM cell elements at the correct point in time. This kind of design also needs a so-called voltage down converter (VDC) to adjust the CVdd and Vdd voltage. This added circuitry and the associated routing required adds about 18% in silicon area to the embedded SRAM block over designs without these features.
There is also the speed concern for the prior art reduced power design. Due to the fact that CVDD will change from high to low from read to write operations, and VCC will change from low to high for the read to write operation, the SRAM array speed is limited, to wait for these voltage states to change. Speed is also another concern for the designs where VDD and CVDD are lowered, because the SRAM cell current is also reduced, the SRAM speed is therefore slower at lower voltage.
The power consumption for this prior art VDC design can improve the peri power to 62.5% (0.78/1.25=62.4%) of the original consumption when the peri voltage is lowered down from 1.1V to 0.85V. However, the array power is increased 25% ((1.25−1)/1=25%), due to the voltage for the array coming from the I/O voltage (1.8V). So the overall power shrinkage is limited to 10% ((2.25−2.03)/2.25=10%) improvement. The SRAM speed/current will also be reduced to around 40%, this is undesirable.
A need thus exists for an area efficient and cost effective solution to the problem of lowering the supply voltage to the SRAM that lowers the power consumption of the SRAM block, while maintaining proper noise margins and ensuring correct data retention.
TABLE 2AreaVcc, min improvementPenalty/Design SolutionMin SuppliedArrayPower PerformanceSRAMMethodology+/−V to VddVccDensityTotal PowerArray PowerPeri PowerSpeedno design solution0 V1.1 VCompared2.2511.251base(compared(comparedbase)base)Prior Art reduced Vcc+/−10%,0.85 V18%/256K2.031.250.780.4Vmax 1.25 V